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abt22v10a5, a7 5v high-speed universal pld device with live insertion capability product specification 1996 dec 16 integrated circuits ic13 data handbook
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 2 1996 dec 16 8531795 17606 description the abt22v10a is a versatile pal ? device fabricated on philips bicmos process known as qubic. the qubic process produces very high speed, 5 volt devices (5.0ns) which have excellent noise immunity . the ground bounce of an output held low while the 9 remaining outputs are switching is less than 1.0v (typical). the abt22v10a outputs are designed to support live insertion/extraction into powered-up systems. the output is specially designed so that during v cc ramp, the output remains 3-stated until v cc 2.1v . at that time, the outputs become fully functional, depending upon device inputs. (see dc electrical characteristics, symbol i pu/pd , page 4). the abt family of devices have virtually no ground bouncee less than 1.0 volts v olp , measured on an unswitched output (9 remaining outputs switching, each with a 50pf load tied to ground). the abt family of devices has been designed with high drive outputs (48ma sink and 16ma source currents), which allow for direct connection to a backplane bus. this feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard 16/4ma plds. philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuseewhether ablowno or aintactoeis at the appropriate and optimal fuse resistance. this dual verify scheme represents a significant improvement over single reference voltage comparison schemes that have been used for bipolar devices since the late 1980' s. the abt22v10a uses the familiar and/or logic array structure, which allows direct implementation of sum-of-products equations. this device has a programmable and array, which drives a fixed or array . the or sum-of-products feeds an aoutput macro cello (omc) that can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. features ? fastest 5v 22v10 ? low ground bounce (<1.0v typical) ? live insertion/extraction permitted ? high output drive capability: 48ma/16ma ? v aried product term distribution with up to 16 product terms per output for complex functions ? metastable hardened flip-flops ? programmable output polarity ? design support provided for third party cad development and programming hardware ? improved fuse verification circuitry increases reliability pin configurations v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gnd a package gnd i7 clk/ i0 i1 i2 i3 i4 i5 gnd i6 i8 i9 i10 gnd i11 f0 f1 f2 f3 f7 f6 f5 f4 f8 f9 a = plastic leaded chip carrier v cc sp00367 pin label descriptions symbol function i1 i11 dedicated input f0 f9 macro cell input/output clk/i0 clock input/dedicated input v cc supply voltage gnd ground ordering information description order code drawing number 28-pin plastic leaded chip carrier abt22v10a5a (5ns device) sot261-3 28-pin plastic leaded chip carrier abt22v10a7a (7.5ns device) sot261-3 ? pal is a registered trademark of advanced micro devices, inc.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 3 absolute maximum ratings 1 symbol parameter ratings unit symbol parameter min max unit v cc supply voltage 2 0.5 +7.0 v dc v in input voltage 2 1.2 v cc + 0.5 v dc v out output voltage 0.5 v cc + 0.5 v dc i in input currents 30 +30 ma i out output currents +100 ma t stg storage temperature range 65 +150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only . functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. except in programming mode. operating ranges symbol parameter ratings unit symbol parameter min max unit v cc supply voltage +4.75 +5.25 v dc t amb operating free-air temperature 0 +75 c thermal ratings temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise ambient to junction 75 c voltage waveform 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368 test load circuit +5v c l r 1 r 2 s 1 c 2 c 1 note: c 1 and c 2 are to bypass v cc to gnd. v cc gnd ck i n i 0 f 0 f n dut oe inputs sp00369
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 4 dc electrical characteristics over operating ranges. symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min max unit input voltage v il low v cc = min 0.8 v v ih high v cc = max 2.0 v v i clamp v cc = min, i in = 18ma 1.2 v output voltage v oh high-level output voltage v cc = min v i = v ih or v il i oh = 32ma 2.0 v v oh high-level output voltage v cc = min v i = v ih or v il i oh = 16ma 2.4 v v ol low-level output voltage v cc = min v i = v ih or v il i ol = 48ma 0.5 v input current i il low v cc = max, v in = 0.4v 10 m a i ih high v cc = max, v in = 2.7v 10 m a i i max input current v cc = max, v in = 5.5v 20 m a output current i pu/pd power-up/down 3-state output current 4 v cc <2.1v; v o = 0.5v to v cc ; v i = gnd or v cc ; oe/oe = x 50 m a v cc = max i ozh output leakage 2 v in = v il or v ih , v out = 2.7v 20 m a i ozl output leakage 2 v in = v il or v ih , v out =0.4v 20 m a i sc short circuit 3 v out = 0.5v 30 220 ma i cc v cc supply current v cc = max, outputs enabled, v i = v cc or gnd; i o = 0 200 ma ground bounce typ max unit v olp minimum dynamic v oh 5 v cc = max, 25 c c l = 50pf (including jig capacitance) 1.0 1.2 v notes: 1. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i ozx or i ix (where x = h or l). 3. no more than one output should be tested at a time. duration of the short-circuit test should not exceed one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is valid for any v cc between 0v and 1.2 v with a transition time up to 10 ms. from v cc = 1.2 to v cc = 5.0v 0.25v a transition time of 100 m s is permitted. x = don't care. 5. guaranteed by design, but not tested. measured holding one output (the output under test) low and simultaneously switching all remianing output from a high to a low state. switch s1 is closed; 50pf load.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 5 ac electrical characteristics 1 4.75v v cc 5.25v; 0 c t amb +75 c symbol parameter test conditions limits unit symbol parameter test conditions abt22v10a5 abt22v10a7 unit conditions min typ max min typ max t pd input or feedback to non-registered output 2 active-low 2.0 4.5 5.0 2.0 6.0 7.5 ns t pd input or feedback to non-registered output 2 active-high 2.0 4.5 5.0 2.0 6.0 7.5 ns t s setup time from input or sp to clock 2.0 1.3 3.5 3.0 ns t sio setup time from feedback to clock 2.25 1.5 3.5 3.0 ns t h hold time 0 0 ns t skewr skew between registered outputs 4, 7 1.0 1.0 ns t co clock to output 2.0 3.5 4.0 2.0 4.5 5.5 ns t cf clock to feedback 3 2.0 4.0 3.0 5.0 ns t ar asynchronous reset to registered output 10.0 10.0 ns t arw asynchronous reset width 6.0 7.5 ns t arr asynchronous reset recovery time 4.0 5.5 ns t spr synchronous preset recovery time 4.5 5.0 ns t wl width of clock low 2.0 3.0 ns t wh width of clock high 2.0 3.0 ns f max maximum frequency; external feedback 1/(t s + t co ) 4 167 208 111 133 mhz f max maximum frequency; internal feedback 1/(t s + t cf ) 4 167 303 125 166 mhz t ea input to output enable 5 8.0 8.0 ns t er input to output disable 5 7.5 7.5 ns capacitance 6 c in input capacitance (pin 2) v in = 2.0v v cc = 5.0v t amb = 25 c f = 1mhz 8 8 pf c in input capacitance (others) v in = 2.0v v cc = 5.0v t amb = 25 c f = 1mhz 4 4 pf c out output capacitance v out = 2.0v f = 1mhz 8 8 pf notes: 1. test conditions: r 1 = 300 w , r 2 =390 w 2. t pd is tested with switch s 1 closed and c l = 50pf (including jig capacitance). v ih = 3v, v il = 0v, v t = 1.5v. 3. calculated from measured f max internal. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. for 3-state output; output enable times are tested with c l = 50pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf. high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 6. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 7. skew is measured with all outputs switching in the same direction.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 6 product features low ground bounce the philips semiconductors bicmos qubic process produces exceptional noise immunity . the typical ground bounce, with 9 outputs simultaneously switching and the 10th output held low , is less than 1.0v. v olp is tested by holding one output (the output uncer test) in the low state and then simultaneously switching all remaining outputs from a high to a low state (each output is loaded with 50pf). the maximum peak voltage on the output under test is guaranteed to be less than 1.2 v olts. live insertion/extraction capability there are some inherent problems associated with inserting or extracting an unpowered module from a powered-up, active system. the abt22v10a outputs have been designed such that any chance of bus contention, glitching or clamping is eliminated. detailed information on this feature is provided in an application note an051: philips plds support live insertion applications . improved fuse verification circuitry increases reliability philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuse whether ablowno or aintacto is at the appropriate and optimal fuse resistance. this dual verify scheme represents a significant improvement over single reference voltage comparisons schemes that have been used for bipolar devices since the late 1980s. detailed information on this feature is provided in an application note entitled dual verify technique increases reliability of plds . programmable 3-stage outputs each output has a 3-stage output buf fer with 3-state control. a product term controls the buffer , allowing enable and disable to be a function of any product of device inputs or output feedback. the combinatorial output provides a bidirectional i/o pin, and may be configured as a dedicated input if the buf fer is always disabled. programmable output polarity the polarity of each macro cell output can be active-high or active-low , either to match output signal needs or to reduce product terms. programmable polarity allows boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity . it can also save ademorganizingo efforts. selection is controlled by programmable bit s 0 in the output macro cell, and af fects both registered and combinatorial outputs. selection is automatic, based on the design specification and pin definitions. if the pin definition and output equation have the same polarity , the output is programmed to be active-high (s 0 = 1). preset/reset for initialization, the abt22v10a has additional preset and reset product terms. these terms are connected to all registered outputs. when the synchronous preset (sp) product term is asserted high, the output registers will be loaded with a high on the next low-to-high clock transition. when the asynchronous reset (ar) product term is asserted high, the output registers will be immediately loaded with a low , independent of the clock. note that preset and reset control the flip-flop, not the output pin. the output level is determined by the output polarity selected. power-up reset all flip-flops power-up to a logic low for predictable system initialization. outputs of the abt22v10a will depend on the programmed output polarity. the v cc rise must be monotonic and the reset delay time is 110 m s maximum. security fuse after programming and verification, abt22v10a designs can be secured by programming the security fuse link. once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer , securing proprietary designs from competitors. when the security fuse is programmed, the array will read as if every fuse is programmed. quality and testability the abt22v10a of fers a very high level of built-in quality . extra programmable fuses provide a means of verifying performance of all ac and dc parameters. in addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields. technology the bicmos abt22v10a is fabricated with the philips semiconductors process known as qubic. qubic combines an advanced, state-of-the-art 1.0 m m (drawn feature size) cmos process with an ultra fast bipolar process to achieve superior speed and drive capabilities. qubic incorporates three layers of al/cu interconnects for reduced chip size, and our proven t i-w fuse technology ensures highest programming yields. programming the abt22v10a is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors snap design software package. abel ? cupl ? and palasm ? 90 design software packages also support the abt22v10a architecture. all packages allow boolean and state equation entry formats, snap , abel and cupl also accept, as input, schematic capture format. output register preload the register on the abt22v10a can be preloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery . the procedure for preloading follows: 1. raise v cc to 5.0v 0.25v. 2. set pin 2 or 3 to v hh to disable outputs and enable preload. 3. apply the desired value (v ilp /v ihp ) to all registered output pins. leave combinatorial output pins floating. 4. clock pin 1 from v ilp to v ihp . 5. remove v ilp /v ihp from all registered output pins. 6. lower pin 2 or 3 to v ilp . 7. enable the output registers according to the programmed pattern. 8. verify v ol /v oh at all registered output pins. note that the output pin signal will depend on the output polarity . abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc. palasm is a registered trademark of amd corp.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 7 metastable characteristics philips provides complete data on the abt22v10a5' s metastable characteristics. while the abt22v10a5 does not employ philips patented metastable immune flip-flop, its metastabel characteristics are still quite favorable relative to competitive devices. for information on metastable immune plds, refer to the datasheets for the abt22v10-7 for 5v applications or the l vt22v10-7 for 3.3v designs. design example suppose a designer wants to use the abt22v10a5 for synchronizing asynchronous data that is arriving at 10mhz (as measured by a frequency counter), in a 5v system that has a clock frequency of 50mhz, at an ambient temperature of 25 c. the next device in the sytem samples the output fo the abt22v10a5 5.5ns after the clock edge to ensure that any metastable conditions that occur have time to resolve to the correct state. the mtbf for this situatio can be calcuclated by using the equation below: mtbf = e(t / t )/t 0 f c f 1 in this formula, f c is the frequency of the clock, f 1 is the average input event frequency, and t is the time after the clock pulse that the output is sampled (t > t co ). t 0 and t are device parameters provided by the semiconductor manufacturer (refer to t able 1 for the abt22v10a5 metastability specifications). t 0 and t are derived from tests and can be most nearly be defined as follows: t is a function of the rate at which a latch in a metastable state resolves that condition. t 0 is a function of the measurement of the propensity of a latch to enter a metastable state. t 0 is also a normalization constant which is a very strong function of the normal propagation dely of the device. in this situation, the f 1 will be twice that data frequency, or 20mhz, because input events consist of both low and high transitions. thus in this case f c is 50mhz, f 1 is 20mhz, t is 85.6ps, t is 5.5ns, and t 0 is 4.55 seconds. using the above formula, the actual mtbf for this situation is 1.76 10 12 seconds, or 55,889 years for the abt22v10a5. table 1. typical values for t and t 0 at various v cc 's and temperatures v cc 0 c +25 c +75 c v cc t t 0 t t 0 t t 0 5.25v 72.00ps 7.20e+01 96.70ps 4.59e01 105.00ps 1.43e01 5.00v 72.80ps 2.06e+02 85.60ps 4.55e+00 100.00ps 8.37e01 4.75v 68.70ps 9.97e+03 81.70ps 4.85e+01 99.80ps 1.29e+00
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 8 logic diagram note: programmable connection. 1 1 0 0 0 1 0 1 d ar q q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 ar sp 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 2 3 4 5 6 7 9 10 11 12 13 14, 15, 8, 22 1, 28 27 26 25 24 23 21 20 19 18 17 16 clk/i0 i1 i2 i3 i4 i5 i6 i7 i10 i8 i9 gnd i11 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 v cc 0 1 9 10 20 21 33 34 48 49 65 66 82 83 97 98 110 111 121 122 130 131 sp00390
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 9 functional diagram output macro cell clk/i0 i1 i11 reset preset f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 programmable and array (44 132) 1 11 8 10 12 14 16 16 14 12 10 8 sp00060 output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell figure 1. functional diagram functional description the abt22v10a allows the systems engineer to implement the design on-chip, by opening fuse links to configure and and or gates within the device, according to the desired logic function. product terms with all fuses opened assume the logical high state; product terms connected to both true and complement of any single input assume the logical low state. the abt22v10a has 12 inputs and 10 i/o macro cells (figure 1). the macro cell allows one of four potential output configurations, registered output or combinatorial i/o, active-high or active-low (see figure 2). the configuration choice is made according to the user' s design specification and corresponding programming of the configuration bits s 0 s 1 . multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the a0o path through the multiplexer . programming the fuse disconnects the control line from gnd and it floats to v cc (1), selecting the a1o path.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 10 output macro cell f 0 1 1 0 0 1 0 0 1 clk 1 ar sp s 1 s 0 s 1 s 0 output configuration 0 = unprogrammed fuse 1 = programmed fuse d q q 0 0 1 1 0 1 0 1 registered/active-low registered/active-high combinatorial/active-low combinatorial/active-high sp00375 figure 2. output macro cell logic diagram f clk ar sp s 0 = 0 s 1 = 0 d q q a. registered/active-low f clk ar sp s 0 = 1 s 1 = 0 d q q b. registered/active-high f s 0 = 0 s 1 = 1 c. combinatorial/active-low d. combinatorial/active-high f s 0 = 1 s 1 = 1 sp00376 figure 3. output macro cell configurations registered output configuration each macro cell of the abt22v10a includes a d-type flip-flop for data storage and synchronization. the flip-flop is loaded on the low -to-high transition of the clock input. in the registered configuration (s 1 = 0), the array feedback is from q of the flip-flop. combinatorial i/o configuration any macro cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (s 1 = 1). in the combinatorial configuration, the feedback is from the pin. variable input/output pin ratio the abt22v10a has twelve dedicated input lines, and each macro cell output can be an i/o pin. buf fers for device inputs have complementary outputs to provide user-programmable input signal polarity.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 11 switching waveforms v t = 1.5v. input pulse amplitude 0v to 3.0v . input rise and fall times 1.5ns max. t s combinatorial output registered output clock to feedback (f max internal) (see path at right) clock width input to output disable/enable asynchronous reset synchronous preset t pd v t v t input or feedback combinatorial output v t v t v t input or feedback clock registered output t s t h t co v t t s + t cf clock logic register clk t s t cf v t t wh clock t wl t er t ea v oh 0.5v v ol + 0.5v input output v t v t v t v t v t t arw t ar t arr clock registered output input asserting asynchronous reset t h v t v t v t v t t spr input asserting synchronous preset clock registered output t co sp00377 clock to feedback
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 12 aando array (i, b) i, b p, d code o state inactive 1 code state code state code state true h l e p, d i, b i, b p, d i, b i, b p, d i, b i, b i, b complement don't care sp00008 i, b i, b i, b i, b note: 1. this is the initial state. preload set-up symbol parameter limits unit symbol parameter min rec max unit v hh super-level input voltage 9.5 9.5 10 v v ilh low-level input voltage 0 0 0.8 v v ihp high-level input voltage 2.4 5.0 5.5 v t d delay time 100 200 1000 ns t i/o i/o valid after pin 2 or 3 drops from v hh to v ilp 100 ns t d v hh v ihp v oh v ol v ilp v ihp v ilp t i/o pins 2, 3 registered outputs clock t d t d t d t d output register preload waveform data in data out v ilp sp00373
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 13 power-up reset the power-up reset feature ensures that all flip-flops will be reset to low after the device has been powered up. the output state will depend on the programmed pattern. this feature is valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below . due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. symbol parameter limits unit symbol parameter min max unit t pr power-up reset time 1 m s t s input or feedback setup time see ac electrical characteristics t wl clock width low see ac electrical characteristics t wl power-up reset waveform 4v v cc t s t pr power registered active-low output clock sp00066 other philips 22v10 devices philips of fers a complete family of 22v10 devices, addressing a wide variety of design applications. this features matrix summarizes the basic features of each specific device. philips 22v10 features matrix pl22v10-10/-15 lvt22v10-7 abt22v10-7 abt22v10a5 abt22v10a7 operating supply voltage +4.75 to +5.25v +3.0 to +3.6v 1 +4.75 to +5.25v +4.75 to +5.25v +4.75 to +5.25v live insertion no yes no yes yes dual verify no yes no yes yes metastability no hardened immune no no source drive capability 4ma (v oh = 2.4v) 16ma (v oh = 2.0v) 16ma (v oh = 2.4v) 16ma (v oh = 2.4v) 16ma (v oh = 2.4v) sink drive capability 16ma (v ol = 0.5v) 32ma (v ol = 0.5v) 48ma (v ol = 0.5v) 48ma (v ol = 0.5v) 48ma (v ol = 0.5v) low ground bounce no yes yes yes yes package availability: plastic dual in-line (n) 24-pin 24-pin 24-pin not available not available plastic leaded chip carrier (a) 24-pin 28-pin 28-pin 28-pin 28-pin plastic small outline large (d) 24-pin 24-pin not available not available not available note: 1. 5 volt compatible i/o. inputs are capable of handling 7v and the outputs can also be pulled up to 7 volts.
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 14 abt22v10a5 timing characterization normalized t co vs temperature (v cc = 5.0v, output capacitance = 50pf, 5 outputs switching) normalized t pd vs temperature (v cc = 5.0v, output capacitance = 50pf, 5 outputs switching) normalized tco vs vcc (temp = 25 c, output capacitance = 50pf, 5 outputs switching) temperature ( c) temperature ( c) supply voltage (v) supply voltage (v) normalized t co normalized t pd normalized t co normalized t pd 1.10 1.05 1.00 0.95 0.90 rise fall normalized tpd vs vcc (temp = 25 c, output capacitance = 50pf, 5 outputs switching) the timing characterization represents the average values of a representative sample for each parameter . the data can be used to derate the max ac characteriza tion based upon the specific user design. philips guarantees the max ac characterization specifications. 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 sp00370 1.10 1.00 0.90 0.80 0 25 50 75 1.10 1.00 0.90 0.80 0 25 50 75 1.10 1.05 1.00 0.95 0.90 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 rise fall rise fall rise fall
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 15 abt22v10a5 timing characterization the timing characterization represents the average values of a representative sample for each parameter . the data can be used to derate the max ac characteriza tion based upon the specific user design. philips guarantees the max ac characterization specifications. delta t co vs number of outputs switching (v cc = 5.0v, temp = 25 c, output capacitance = 50pf) delta t pd vs number of outputs switching (v cc = 5.0v, temp = 25 c, output capacitance = 50pf) delta t co vs output capacitance (v cc = 5.0v, temp = 25 c, 5 outputs switching) delta t pd vs output capacitance (v cc = 5.0v, temp = 25 c, 5 outputs switching) co pd pd co 0.20 0.0 0.40 0.80 1.00 1.40 1.80 1 2 3 4 5 6 7 8 9 10 number of outputs switching number of outputs switching output capacitance output capacitance delta t (ns) delta t (ns) delta t (ns) delta t (ns) sp00371 0.20 0.60 rise fall 1.20 1.60 0.20 0.0 0.40 0.80 1.00 1.40 1.80 1 2 3 4 5 6 7 8 9 10 0.20 0.60 1.20 1.60 rise fall 10 50 100 200 400 3.50 2.50 0.50 1.50 4.50 1.50 0.50 10 50 100 200 400 3.50 2.50 0.50 1.50 4.50 1.50 0.50 rise fall rise fall
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 16 plcc28: plastic leaded chip carrer; 28 leads; pedestal sot261-3
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 17 notes
philips semiconductors product specification abt22v10a5, a7 5v high-speed universal pld device with live insertion capability 1996 dec 16 18 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury . philips semiconductors and philips electronics north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

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